A tunnel field effect transistor (TFET) is a transistor that controls turning on and off of devices by using a tunnel current generated at a PN junction of a semiconductor or a Schottky junction between metal and a semiconductor.
Conventionally, the tunnel field effect transistor has had a problem that its on-current is less than that of the existing MOSFET (Metal-Oxide Semiconductor FET). To handle such a problem, a type of tunnel field effect transistor having a vertical PN junction in a channel region on a source side has been proposed. According to this vertical PN junction, a P-type semiconductor and an N-type semiconductor are adjacent to each other in a direction vertical to a surface of a semiconductor substrate (hereinafter, also “vertical direction”).
However, according to the conventional tunnel field effect transistor with a vertical PN junction, a horizontal PN junction is also provided immediately below a gate electrode. In the horizontal PN junction, a P-type semiconductor and an N-type semiconductor are adjacent to each other in a horizontal direction with respect to the surface of a semiconductor substrate (hereinafter, also “horizontal direction”). Because the horizontal PN junction is provided immediately below the gate electrode, a gate voltage applies a larger electric field to the horizontal PN junction than to the vertical PN junction in this tunnel field effect transistor. Therefore, band-to-band tunneling at the horizontal PN junction occurs earlier than that at the vertical PN junction. Consequently, such a tunnel field effect transistor reduces its S-factor.
A conductivity type of a channel region on a drain side is the same as that of a drain diffusion layer. A conductivity type of the channel region on the source side is also the same as that of the drain diffusion layer. Therefore, when a drain voltage is applied, an electric field is applied to PN junctions and band-to-band tunneling occurs, so that an off-leakage current is increased.
Furthermore, when a drain voltage is applied, a reverse bias is applied between a source diffusion layer below the channel region on the source side and the drain diffusion layer, so that a junction leakage current is generated. As a result, the off-leakage current is further increased.